AMD EPYC “Venice” To Launch In 2026 As One Of The First 2nm Zen 6 CPUs Manufactured By TSMC

AMD has officially confirmed that its upcoming EPYC “Venice” processor line will be among the first products manufactured using TSMC’s advanced 2nm (N2) process node. This announcement celebrates the long-standing partnership between AMD and TSMC and signifies a major step forward in high-performance computing (HPC) technology. The Venice series, based on AMD’s future Zen 6 and Zen 6c architectures, is expected to launch in 2026 and will mark a generational leap in CPU design and manufacturing.

According to AMD, the EPYC Venice processors have reached the “tape-out” stage, meaning their designs have been finalized and are now ready to begin manufacturing. This milestone positions Venice as the industry’s first HPC-oriented chip to reach tape-out using the N2 process. The upcoming EPYC 9006 family will follow the current EPYC 9005 “Turin” generation and will likely debut in the latter half of 2026, following AMD’s typical release cadence.

✅ Our next-gen EPYC processor, codenamed “Venice,” is the first HPC product in the industry to be taped out and brought up on the TSMC advanced #2nm (N2) process technology.

— AMD (@AMD) April 14, 2025

Although AMD has not disclosed detailed specifications of the Zen 6 architecture, expectations are high for significant performance gains over Zen 5. Improvements may include increased core counts and architectural refinements aimed at further optimizing efficiency and computational power. These advancements will cater to demanding HPC workloads such as scientific research, simulations, and large-scale data processing.

TSMC’s N2 process introduces several key innovations, most notably the transition to GAAFET (Gate-All-Around Field-Effect Transistor) technology. GAAFETs offer improved control over electrical current, leading to greater power efficiency and higher transistor density. Additionally, the technology allows chip designers to fine-tune transistor dimensions for performance, power, or balanced optimization, offering enhanced flexibility in chip engineering.

Manufactured in the US

#TogetherWeAdvance: Our deep partnership with TSMC is bringing leading-edge technologies to market that will power the most demanding data center applications of the future. https://t.co/vFLf3v7JuS pic.twitter.com/a1ilYdKf7S

— AMD (@AMD) April 14, 2025

In another strategic move, AMD has confirmed that its current EPYC 9005 series has been validated for production at TSMC’s Fab 21 facility in Arizona, USA. This factory is TSMC’s first in the U.S. and part of a broader initiative to diversify global semiconductor production. Fab 21 specializes in 5nm and 4nm processes, and while no exact timeline was shared, production of the EPYC 9005 chips in Arizona is expected to begin later in 2025, with further announcements anticipated.

Filed in Computers. Read more about AMD, CPU and TSMC.